Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods

In this paper we propose a novel approach to the synthesis of minimal-sized lattices, based on the decomposition of logic functions. Since the decomposition allows to obtain circuits with a smaller area, our idea is to decompose the Boolean functions according to generalizations of the classical Shannon decomposition, then generate the lattices for each component function, and finally implement the original function by a single composed lattice obtained by glueing together appropriately the lattices of the component functions. In particular we study the two decomposition schemes defining the bounded-level logic networks called P-circuits and EXOR-Projected Sums of Products (EP-SOPs). Experimental results show that about 34% of our benchmarks achieve a smaller area when implemented using the P-circuit decomposition for switching lattices, with an average gain of at least 25%, and about 27% of our benchmarks achieve a smaller area when implemented using the EP-SOP decomposition, with an average gain of at least 22%

A 28-nm CMOS pixel read-out ASIC for real-time tracking with time resolution below 20 ps

We present the development of a test ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 μm, The ASIC is conceived as the first prototype in a series, capable to read-out pixels with timing capabilities in the range of 30 ps and below. Each pixel is endowed with a charge amplifier, a discriminator and a Time-to-Digital-Converter, capable of time resolutions below 20 ps and read-out rates (per pixel) around 3 MHz. The timing performance are obtained respecting a power budget of about 50 μW per pixel, corresponding to a power density of approximately 2 W/cm 2 · This feature makes the Timespot1 approach an interesting solution for vertex detectors of the next generation of colliders, where high space and time resolutions will be mandatory requirements to cope with the huge amount of tracks per event to be detected and processed

Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a $32 \times 32$ pixel matrix with a pitch of $55 ~ \mu m$. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below $50 ~ ps_\text{rms}$ and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digital Converter with time resolution indicatively of $22.6 ~ ps_\text{rms}$ and maximum readout rates (per pixel) of $3 ~ MHz$. To respect system-level constraints, the timing performance has been obtained keeping the power budget per pixel below $40 ~ \mu W$. The ASIC has been tested and characterised in the laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched $32 \times 32$ pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance

CMOS IC RADIATION HARDENING BY DESIGN

Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design

Impact of package parasitics on crosstalk in mixed-signal ICs

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A realistic model of bonding and package parasitics has been derived to study digital switching noise injected through bonding interconnections. Simulations results indicate that disturbances due to switching currents in digital blocks propagate through the substrate and affect analog voltages, thus degrading circuit performance. Test structures have been integrated into a test chip mounted with different technologies, in order to compare the measurements on test chips. Measurements confirm simulation results. Chip-on-board mounting technology has better performance with respect to chip-in-package, due to the reduction of parasitic elements

The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking

A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time- to-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 μm × 55 μm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders

The ASTAROTH project

The most discussed topic in direct search for dark matter is arguably the verification of the DAMA claim. In fact, the observed annual modulation of the signal rate in an array of NaI(Tl) detectors can be interpreted as the awaited signature of dark matter interaction. Several experimental groups are currently engaged in the attempt to verify such a game-changing claim with the same target material. However, all present-day designs are based on a light readout via Photomultiplier Tubes, whose high noise makes it challenging to achieve a low background in the 1-6 keV energy region of the signal. Even harder it would be to break below 1 keV energy threshold, where a large fraction of the signal potentially awaits to be uncovered. ASTAROTH is an R\&D project to overcome these limitations by using Silicon Photomultipliers (SiPM) matrices to collect scintillation light from NaI(Tl). The all-active design based on cubic crystals is operating in the 87-150 K temperature range where SiPM noise can be even a hundred times lower with respect to PMTs. The cryostat was developed following an innovative design and is based on a copper chamber immersed in a liquid argon bath that can be instrumented as a veto detector. We have characterized separately the crystal and the SiPM response at low temperature and we have proceeded to the first operation of a NaI(Tl) crystal read by SiPM in cryogeny.Comment: proceedings of the LRT 2022 conferenc

A Hydrogenated amorphous silicon detector for Space Weather Applications

The characteristics of a hydrogenated amorphous silicon (a-Si:H) detector are presented here for monitoring in space solar flares and the evolution of large energetic proton events up to hundreds of MeV. The a-Si:H presents an excellent radiation hardness and finds application in harsh radiation environments for medical purposes, for particle beam characterization and in space weather science and applications. The critical flux detection threshold for solar X rays, soft gamma rays, electrons and protons is discussed in detail.Comment: 32 pages, 13 figures, submitted to Experimental Astronom

Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparison of about 1 Mbit per second. The parallel input data rate is 100 MHz. Thanks to the XORAM cell and to the design optimization, the AM06 consumes about 1 fJ/bit per comparison. The AM is tailored for on-line track finding in physics experiments; however, it is suitable also for interdisciplinary applications (i.e., general purpose image filtering and analysis). In future we plan to design a more powerful and flexible chip at 28 nm CMOS